System and method for testing and debugging a multiprocessing interrupt controller
US5790871A · kind A · utility
24Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 1996 |
| Grant date | Aug 4, 1998 |
| Priority date | — |
| Expiry date | May 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system comprising at least one processing unit, a plurality of I/O devices, and a central interrupt control unit intercoupling the processing unit and the plurality of I/O devices. The central interrupt control unit is configured to receive interrupt signals from the I/O devices and is configured to distribute said interrupt signals to the processing unit. The central interrupt control unit is further configured to provide a signal simulative of an interrupt signal to simplify the testing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.