System for providing tight program/erase speeds that are insensitive to process variations
US5793249A · kind A · utility
11Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system and method of enhancing the yield of flash memory circuit is disclosed. The method comprises performing a diagonal erase of a select group of memory cells on a wafer during sort. If the memory cells do not erase in a satisfactory manner, the control voltage applied to the memory cell is adjusted based on the memory cell's erase time. The circuitry for providing the adjustment voltage includes trimming circuitry for an incrementally increasing the applicable control of voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.