Dynamic dielectric protection circuit for a receiver
US5793592A · kind A · utility
15Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 1997 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | May 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A topology for arranging a plurality of transistors between a signal source and an off-chip receiver, using a single power supply voltage. A pass through NFET has a gate controlled by a network comprised of two transistors arrayed between the power supply voltage and the drain of the NFET, which limits overshoots to the power supply voltage and reduces undershoots. Further reduction of undershoots is accomplished by an additional network of transistors, optimally including a PFET in series with the pass through NFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.