Using floating gate devices as select gate devices for NAND flash memory and its bias scheme
US5793677A · kind A · utility
38Cited by
5References
10Claims
0Family size
Inventors
Key dates
| Filing date | Jun 18, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Jun 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates programming of selected floating gate devices while successfully inhibiting the programming of unselected devices, without the need for growing multiple thicknesses of oxides. The preferred embodiment of the present invention utilizes a multiple select gate device. In particular, the select gate device is preferably a dual floating gate device rather than the conventional transistor (or device functioning as a conventional transistor) used in the current Flash memory systems as a select gate device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.