Method for simplifying the manufacture of an interlayer dielectric stack
US5795820A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for simplifying the manufacture of an interlayer dielectric where local interconnects are utilized. The invention utilizes a separate LI stack and first contact stack deposition and etch. In the first step, a layer of oxide etch stop and a layer of TEOS oxide are deposited to form a first LI stack. This stack is then contact etched, filled, and polished. A first contact stack is then formed by deposition of a doped silane oxide layer that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop, a second layer of undoped TEOS oxide, and a final layer of doped silane oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.