Inventor · Saratoga, CA, US

Nick Kepler

31Patents
14h-index
16Co-inventors
70Inventor score

Filing activity: Jul 1, 1996 → Apr 23, 2001

Most-cited inventions

PatentTitleAreaCited byStatus
US6037671A Stepper alignment mark structure for maintaining alignment integrity Emerging Cross-Sectional Technologies 61 Expired
US5930645A Shallow trench isolation formation with reduced polish stop thickness Electricity 54 Expired
US6171962A Shallow trench isolation formation without planarization mask Electricity 38 Expired
US6150243A Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer Electricity 32 Expired
US6074927A Shallow trench isolation formation with trench wall spacer Electricity 26 Expired
US6100145A Silicidation with silicon buffer layer and silicon spacers Electricity 23 Expired
US6238986A Formation of junctions by diffusion from a doped film at silicidation Electricity 22 Expired
US6046104A Low pressure baked HSQ gap fill layer following barrier layer deposition for high integrity borderless vias Electricity 22 Expired
US6239031A Stepper alignment mark structure for maintaining alignment integrity Emerging Cross-Sectional Technologies 21 Expired
US6255214A Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of source and drain regions Electricity 18 Expired
US6030862A Dual gate oxide formation with minimal channel dopant diffusion Electricity 17 Expired
US6096599A Formation of junctions by diffusion from a doped film into and through a silicide during silicidation Emerging Cross-Sectional Technologies 17 Expired
US6130467A Shallow trench isolation with spacers for improved gate oxide quality Electricity 16 Expired
US6274511A Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer Electricity 14 Expired
US5795820A Method for simplifying the manufacture of an interlayer dielectric stack Electricity 14 Expired
US6143624A Shallow trench isolation formation with spacer-assisted ion implantation Emerging Cross-Sectional Technologies 13 Expired
US6599810B1 Shallow trench isolation formation with ion implantation Electricity 13 Expired
US6162689A Multi-depth junction formation tailored to silicide formation Electricity 13 Expired
US6156615A Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions Electricity 13 Expired
US6165903A Method of forming ultra-shallow junctions in a semiconductor wafer with deposited silicon layer to reduce silicon consumption during salicidation Electricity 13 Expired
US6124183A Shallow trench isolation formation with simplified reverse planarization mask Electricity 13 Expired
US6514844B1 Sidewall treatment for low dielectric constant (low K) materials by ion implantation Electricity 13 Expired
US5970363A Shallow trench isolation formation with improved trench edge oxide Electricity 10 Expired
US5970362A Simplified shallow trench isolation formation with no polish stop Electricity 10 Expired
US6169005A Formation of junctions by diffusion from a doped amorphous silicon film during silicidation Electricity 10 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.