Method of chemically mechanically polishing an electronic component
US5795826A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Jul 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming interlevel studs of at least two different materials in an insulating layer on a semiconductor wafer. After forming an insulating layer of BPSG on a Front End of the Line (FEOL) structure, the BPSG layer is chem-mech polished. Vias are formed through the BPSG layer in array areas. A thin doped poly layer is deposited on the surface of the BPSG layer. The structure is annealed and vias are formed in support areas. Dopants are implanted into support areas through the vias. After annealing to diffuse implanted dopant, a metal layer is formed on the poly layer. Then, the structure is chem-mech polished back to the poly layer. A final chem-mech polish step removes the poly layer, leaving metal studs in the support areas and poly-lined metal cored studs in the array areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.