Row decoder circuit for PMOS non-volatile memory cell which uses electron tunneling for programming and erasing
US5796656A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Feb 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.