Memory array built-in self test circuit for testing multi-port memory arrays
US5796745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Jul 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array. The combination of programmable data, programmable read/write sequences, programmable address counter, and programmable frequency allows for determistic testing of a multi-por…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.