Highly pipelined bus architecture
US5796977A · kind A · utility
69Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.