Hierarchical fault modeling system and method
US5796990A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for generating a fault model for a logic circuit includes a data storage device for storing information relative to fault models or primitive elements in a logic circuit and for storing fault models for each level of design in a hierarchical logic circuit, a processor for processing the stored information relative to primitives and lower level fault models in the hierarchy for generating fault models for each succeeding higher level of design in the hierarchy, an input device for operator input of information to modify primitive fault models and a display subsystem for displaying various aspects of the hierarchical fault model generated in accordance with the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.