Inventor · Williston, VT, US

Peter Wohl

31Patents
12h-index
20Co-inventors
81Inventor score

Filing activity: Dec 20, 1994 → Jun 13, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6385750B1 Method and system for controlling test data volume in deterministic test pattern generation Physics 54 Expired
US6950974B1 Efficient compression and application of deterministic patterns in a logic BIST architecture Physics 51 Expired
US7237162B1 Deterministic BIST architecture tolerant of uncertain scan chain outputs Physics 41 Expired
US6993694B1 Deterministic bist architecture including MISR filter Physics 41 Expired
US6247165A System and process of extracting gate-level descriptions from simulation tables for formal verification Physics 38 Expired
US6807646B1 System and method for time slicing deterministic patterns for reseeding in logic built-in self-test Physics 34 Expired
US6148436A System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation Physics 30 Expired
US7823034B2 Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit Physics 29 Active
US5668492A Integrated circuit clocking technique and circuit therefor Physics 19 Expired
US6453437B1 Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation Physics 16 Expired
US5796990A Hierarchical fault modeling system and method Physics 15 Expired
US7814444B2 Scan compression circuit and method of design therefor Physics 12 Active
US7979763B2 Fully X-tolerant, very high scan compression scan test systems and techniques Physics 10 Active
US5508641A Integrated circuit chip and pass gate logic family therefor Electricity 8 Expired
US7958472B2 Increasing scan compression by using X-chains Physics 8 Active
US6959272B2 Method and system for generating an ATPG model of a memory from behavioral descriptions Physics 6 Expired
US7882410B2 Launch-on-shift support for on-chip-clocking Physics 6 Active
US8645780B2 Fully X-tolerant, very high scan compression scan test systems and techniques Physics 4 Active
US8464115B2 Fully X-tolerant, very high scan compression scan test systems and techniques Physics 3 Active
US8429473B2 Increasing PRPG-based compression by delayed justification Physics 2 Active
US9157961B2 Two-level compression through selective reseeding Physics 2 Active
US9171123B2 Diagnosis and debug using truncated simulation Physics 1 Active
US8549372B2 ATPG and compression by using majority gates Physics 1 Active
US10908213B1 Reducing X-masking effect for linear time compactors Physics 1 Active
US12277372B2 Multi-cycle test generation and source-based simulation Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.