Linewidth metrology of integrated circuit structures
US5804460A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/888
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Illustratively, the present invention includes a method of integrated circuit manufacturing which includes forming a raised topological feature upon a first substrate. A portion of the raised feature is removed, thereby exposing a cross sectional view of the raised feature with the substrate remaining substantially undamaged. The cross sectional view has a critical dimension. The critical dimension of the cross sectional view is measured using a first measuring instrument. Then the critical dimension is measured using a second measuring instrument. The measurements of the first and second measuring instruments are correlated. Then, using the second measuring instrument, raised features via plurality of second substrates are measured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.