Process for manufacturing a packaged semiconductor having a divided leadframe stage
US5804468A · kind A · utility
36Cited by
10References
4Claims
0Family size
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Key dates
| Filing date | Nov 21, 1995 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Nov 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.