Automatic synthesis of integrated circuits employing boolean decomposition
US5805462A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of automatic synthesis of an integrated circuit, comprising the steps, performed by a programmed machine, of storing a Boolean expression which expresses a combinatorial part of the said integrated circuit, factorizing the Boolean expression and mapping the factorized Boolean expression into a representation of said integrated circuit in hardware terms. The step of factorizing comprises computing a zero-suppressed binary decision diagram unique to and representing the Boolean expression; computing, from said ZBDD, candidate divisors of said expression; selecting candidate divisors; and dividing the Boolean expression by the candidate divisor. The selection of candidate divisors includes computing attributed value on the basis of the saving of literals. The method includes the use of implicit division comprising computing upper and lower bounds for a remainder and then a quotient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.