Integrated high-performance decoupling capacitor
US5811868A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance. Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip. Very precise decoupling of selected areas in the chip circuit can be achieved by forming precise and multiple metal deposits of either the same size or of varying sizes to define specific capacitances and individually connecting these deposits to the circuit areas needing the precise decoupling capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.