Cache sub-array method and apparatus for use in microprocessor integrated circuits
US5812418A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Oct 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.