System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers
US5815458A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline. In some embodiments, one set of wordline drivers (positioned along one side of the array) drives the even-numbered wordlines, another set of wordline drivers (positioned along the opposite side of the array) drives the odd-numbered wordlines, and the system exchanges the bitline addresses of the first packet and last packet (or the first N bytes of the first packet and the last N bytes of the last packet) of each sector to be wr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.