System and method for reconfiguring configuration registers of a PCI bus device in response to a change in clock signal frequency
US5815734A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 1997 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Jun 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is described for facilitating operation of a peripheral bus, such as a PCI bus, at a higher clock frequency. Each of the devices resident on the PCI bus include certain configuration registers, including MIN.sub.-- GNT and MAX.sub.-- LAT, which provide configuration parameters to various system resources. In addition, each of the devices resident on the PCI bus include a status register with a dedicated 66 MHzCAPABLE bit. The dedicated status bit indicates whether the PCI device is capable of operating in a 66 MHz environment. As a result, each device can be polled during system initialization to determine if all of the PCI devices will support 66 MHz operation. If the system determines that the clock frequency will change due to a change in the system configuration (such as PCI devices being added or removed from the PCI bus), the configuration registers of each of the PCI devices can be modified to insure proper operation at the new clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.