Area and time efficient extraction circuit
US5815736A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a data word extraction circuit that receives n data words DW.sub.x (for x equal 0 through n-1), where each of the data words DW.sub.x having m bit positions BP.sub.y (for y=0 through m-1). The circuit provides at least one of the data words DW.sub.x to an extraction circuit output responsive to an extraction indicator signal. Specifically, a group of data selector elements DSE.sub.y, each corresponding to a separate one of the bit positions BP.sub.y in the received data words. Each data selector element includes a data output DO.sub.y and a plurality of data inputs DI.sub.x. Each data input DI.sub.x is connected to receive a bit from the bit position BP.sub.y to which the data selector element DSE.sub.y corresponds, of a data word DW.sub.x to which the data input DI.sub.x corresponds. A select input is responsive to the extraction indicator signal such that the data selector element DSE.sub.y provides, at the data output, the bit received at one of the data inputs DI.sub.x that corresponds to the extraction indicator signal. The bits provided at the data outputs of the group of data selector elements are collectively provided to the extraction circuit outpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.