Block-level wordline enablement to reduce negative wordline stress
US5818764A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Feb 6, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is provided for supplying a negative erasing voltage onto the wordlines of selected blocks in an array of floating gate memory cells. The circuit includes a voltage circuit, which has a plurality of local outputs, each of which connects to wordlines of an associated block of floating gate memory cells. A block selector circuit is coupled to the local outputs of the voltage circuit and selectively switches each of the local outputs to apply either an erasing voltage or a non-erasing voltage onto the wordlines of the associated block of floating gate memory cells. Negative wordline stress is thus reduced for wordlines of unselected blocks which receive a less negative, non-erasing voltage during block erase operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.