Automatic test circuitry with non-volatile status write
US5818848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile sta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.