TFT with self-align offset gate
US5821564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | May 23, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A PMOS thin film transistor (TFT) with self-align offset region for SRAM application is described. A source and a drain regions are above the gate region. A channel region is formed offset from the gate. An offset region is formed in the channel region having a length of 0.3 to 0.4 .mu.m. The key point of the present invention is the novel offset design of PMOS-TFT as load elements in an SRAM cell. Unlike the conventional offset design which is outside the gate, the offset region of the present invention is a disconnection region inside the gate which can be easily formed by so called self-align technique. Since the gate has a disconnected portion in the offset region, the trench-like profile of the offset region makes the load resistance in the offset region much higher to effectively reduce the leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.