Dual buffer flash memory architecture with multiple operating modes
US5822245A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Mar 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory array architecture comprising a flash memory array, first and second memory buffer, and I/O interface circuit which has several operating modes which permit data to be read from the flash memory array, several operating modes which permit data to be programmed into the flash memory array, and a mode for rewriting the data in the flash memory array. In the four read modes, one of the pages stored in the flash memory array is read, the data stored in either of first or second memory buffers is read, the data in one of the pages of data stored in the flash memory array is read and then written into either of first or second memory buffers, the data in one of the pages of data stored in the flash memory array is read and then compared to the data read from either of first or second memory buffers. In the four write modes, data from an input stream is written into a selected first or second memory buffer, one of the pages of data stored in the flash memory array is erased, and then in the same cycle, data in either of first or second memory buffers is written into the erased page in the flash memory array, data in either of first or second memory buffers is written into a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.