Apparatus and method for determining if an operand lies within an expand up or expand down segment
US5822786A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1994 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dedicated parallel comparators perform expand up or expand down segment limit checks for memory accesses. A first three-input comparator has as inputs the complement of the segment limit, the effective address of the first byte of the access, and an configurable third input. For expand up segments, the configurable third input is set to one less than the memory access size. A carry out of the first comparator is generated, and thereby a limit fault indicated, if the address of the last byte of the access exceeds the segment limit. For expand down segments, the configurable third input is set to zero. In this case, the lack of a carry out of the first comparator indicates that the address of the first byte of the access exceeds the segment limit. For expand down segments a parallel second two-input comparator is also used. The second comparator has as inputs the effective address and a hybrid second input. A least significant portion of the hybrid input is set to one less than the memory access size. Multiple bits in a most significant portion of the hybrid input reflect the complement of the segment descriptor's B-bit. The second comparator generates a carry whenever the address of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.