Insulated wafer spacing mask for a substrate support chuck and method of fabricating same
US5825607A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | May 8, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/6831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulated wafer spacing mask for supporting a workpiece in a spaced apart relation to a workpiece support chuck. More specifically, the wafer spacing mask contains a plurality of support members deposited upon an insulating material located between the wafer spacing mask and the support surface of the chuck. The support members maintain a wafer, or other workpiece, in a spaced apart relation to the support surface of the chuck. The distance between the underside surface of the wafer and the chuck is defined by the thickness of the support members. This distance should be larger than the expected diameter of contaminant particles that may lie on the surface of the chuck. In this manner, the contaminant particles do not adhere to the underside of the wafer and current leakage through the wafer is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.