Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit
US5825658A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1995 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Sep 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable. The computer aided design system then automatically verifies that the integrated circuit satisifies the specified timing constraints. During the timing constraint verification process, for mutli-clock timing cons…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.