Simplified masking process for programmable logic device manufacture

US5830795A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Sunil Mehta · Rumford, US
• Radu Barsan · Saratoga, US

Key dates

• Filing date: Jun 10, 1996
• Grant date: Nov 3, 1998
• Expiry date: Jun 10, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

A process for forming CMOS transistors on a semiconductor substrate, wherein the plurality of transistors includes high-voltage N-channel and high-voltage P-channel transistors, and low-voltage N-channel and low-voltage P-channel transistors, wherein a tunnel oxide of a first thickness is required and a gate oxide of a second thickness is required is provided. The process comprises the steps of: forming a thick gate oxide on the surface of the substrate; forming a low voltage n-channel transistor mask, the mask including a plurality of windows exposing first portions of the thick gate oxide; implanting an n-type dopant into the substrate through said windows and through the thick gate oxide layer to form an n-dopant implant region; etching a first portion of the thick gate oxide exposing the surface of the substrate overlying the n-dopant implant region; stripping the low voltage n-channel mask; forming a low voltage p-channel transistor mask, the mask including a plurality of windows exposing the second portions of the thick gate oxide; implanting a p-type dopant into the substrate through said windows and through the thick gate oxide layer; etching a second portion of the thick g…