Non-volatile memory device having optimized management of data transmission lines
US5831891A · kind A · utility
0Cited by
7References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1997 |
| Grant date | Nov 3, 1998 |
| Priority date | — |
| Expiry date | Mar 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus that runs from one end of the memory device to the other, one or more source structures that exist externally and internally to the memory device, and a timer means. The timer means is adapted to time-control the independent and exclusive access of the external and internal source structures, within a same memory cycle, to the internal bus for the transmission of data, controls, and functions, from one end of the memory to the other over the internal bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.