Antonio Barcella
13Patents
5h-index
8Co-inventors
51Inventor score
Filing activity: May 2, 1995 → Dec 27, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6009041A | Method and circuit for trimming the internal timing conditions of a semiconductor memory device | Physics | 27 | Expired |
| US5659498A | Unbalanced latch and fuse circuit including the same | Electricity | 13 | Expired |
| US6363015B1 | Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method | Physics | 10 | Expired |
| US5959902A | Voltage level shifter device, particulary for a nonvolatile memory | Physics | 5 | Expired |
| US5715204A | Sense amplifier with hysteresis | Physics | 5 | Expired |
| US6075718A | Method and device for reading a non-erasable memory cell | Physics | 5 | Expired |
| US5815437A | Data input/output managing device, particularly for a non-volatile memory | Physics | 3 | Expired |
| US5821788A | Zero consumption power-on-reset | Physics | 3 | Expired |
| US6700226B2 | Multi-emitter bipolar transistor for bandgap reference circuits | Electricity | 2 | Expired |
| US5841728A | Hierarchic memory device having auxiliary lines connected to word lines | Physics | 1 | Expired |
| US5831891A | Non-volatile memory device having optimized management of data transmission lines | Physics | 0 | Expired |
| US5754483A | Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders | Physics | 0 | Expired |
| US6438669B2 | Timesharing internal bus, particularly for non-volatile memories | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.