Page mode program, program verify, read and erase verify for floating gate memory device with low current page buffer
US5835414A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page mode flash memory or floating gate memory device, includes a page buffer based on low current bit latches. The low current bit latches enable efficient program, program verify, read and erase verify processes during page mode operation. The array includes bit lines coupled with corresponding columns of cells in the array, and wordlines coupled with corresponding rows of cells in the array. Bit latches are coupled to respective bit lines to provide a page buffer. Control logic executes the steps of (1) setting a set of bit lines to a pre-charge voltage level (such as VDD or ground); (2) isolating the pre-charged bit line, applying a wordline voltage to the wordline of the page of cells to be sensed; and (3) responding to changes in the voltage levels of the bit lines (which are discharged if a memory cell is conductive) in response to the wordline voltage, to store a constant in the bit latches coupled to the bit lines on which the voltage levels of the bit lines passes a determinate threshold during the step of applying a wordline voltage. The bit lines are connected to the gate terminal of a pass transistor, so that when the turn on threshold of the pass transistor is passe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.