EDRAM with integrated generation and control of write enable and column latch signals and method for making same
US5835442A · kind A · utility
3Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1996 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Mar 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EDRAM device includes an EDRAM memory array on a semiconductor chip. A row enable signal generator and a column address latch signal generator are provided on the same semiconductor chip for generating row enable and column address latch signals for application to the EDRAM memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.