Debugging a processor using data output during idle bus cycles
US5838897A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1996 |
| Grant date | Nov 17, 1998 |
| Priority date | — |
| Expiry date | Feb 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for outputting processor state information during idle bus cycles to facilitate the diagnosing and debugging of a processor. The processor includes a plurality of external pins for communicating data from the processor; a visibility register for selecting one of a plurality of modes which identifies processor state information to output onto the plurality of external pins; and a bus interface unit for communicating data to the external pins of the processor and for detecting an idle bus cycle. The bus interface unit outputs processor state information according to the identified mode onto the plurality of external pins in response to detecting an idle bus cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.