Method of fabricating very high gain heterojunction bipolar transistors
US5840612A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Aug 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
Abstract
A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (.beta.) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.