Method of charging and discharging floating gage transistors to reduce leakage current
US5841701A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 1997 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Jan 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for improving the endurance and reliability of a floating gate transistor often used in memory applications by controlling the electric field induced across the tunnel oxide region of the floating gate when discharging electrons from the floating gate. The method comprises the steps of: allowing the active region to ground; and applying a program voltage to the floating gate over a period of time and at a magnitude, by increasing the voltage from zero volts to the magnitude over a first period of at least 1 millisecond (ms.), maintaining the voltage at the magnitude for a second period of around 10 ms.-100 ms. sufficient to place charge on the floating gate, and decreasing the voltage from the magnitude during a third period to zero volts in not greater than 50 microseconds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.