Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing

US5846884A · kind A · utility

Assignees

• Siemens Aktiengesellschaft · DE
• International Business Machines Corporation · US
• Kabushiki Kaisha Toshiba · JP

Inventors

• Munir D. Naeem · Poughkeepsie, US
• Stuart M. Burns · Ridgefield, US
• Nancy Anne Greco · Lagrangeville, US
• STEVE GRECO · Lagrangeville, US
• Virinder Grewal · Wappingers Falls, US
• Ernest N. Levine · Poughkeepsie, US
• Masaki Narita · Tokyo, JP
• Bruno Spuler · Wappingers Falls, US

Key dates

• Filing date: Jun 20, 1997
• Grant date: Dec 8, 1998
• Expiry date: Jun 20, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32136
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.