Final stage clock buffer in a clock distribution network
US5850150A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1996 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A final stage clock buffer for use in a clock distribution network in a circuit with scan design includes a demultiplexer circuit and a control circuit. The buffer receives an input clock signal and outputs a clock signal and a scan clock signal. The buffer can operate in a functional mode, a scan mode and a hold mode. The demultiplexer circuit receives the input clock signal and a scan enable signal. The scan enable signal, when asserted, causes the buffer to enter the scan mode. In the scan mode, the demultiplexer circuit propagates the input clock signal to a scan clock terminal and a constant logic level to a clock terminal. When the scan enable signal is deasserted, the demultiplexer circuit propagates the input clock signal to the clock terminal and a constant logic level to the scan clock terminal. The control circuit receives a chip-enable signal. When the chip-enable signal is asserted while the scan signal is deasserted, the buffer enters the functional mode. The asserted chip-enable signal causes the control circuit to allow the input clock signal to continue to propagate to the clock terminal. When both the chip-enable signal and the scan signal are deasserted, the buff…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.