Burst EDO memory address counter
US5850368A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1997 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Sep 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter comprised of two flip flops and a multiplexer produces a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). Input addresses in combination with a sequence select signal are logically combined to produce a multiplexer select input which selects between true and compliment outputs of a first flip flop to couple to an input of a second flip flop to specify a toggle condition for the second flip flop. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access. A transition of the Read/Write control line during a burst access will terminate the burst access and initialize the device for another burst access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.