Method and apparatus for reducing cache snooping overhead in a multilevel cache system
US5850534A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other memory accessing device. Each intermediate level cache is connected to a cache level one level above and below that cache. The highest cache level detects a memory access on a shared memory bus, and determines if that memory access resides in that cache. If there is a hit in that cache, the highest cache level checks a hit flag for every storage location within that highest level cache to determine if the memory access also hits a storage location within the next lower cache level. If there is a hit in the next lower cache level, that cache also checks a hit flag for every storage location within that cache to determine if the memory access also hits a storage location within the next lower cache level. This process continues until the memory access does not hit a particular cache level or until the lowest cache level is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.