Process for packaging a semiconductor die using dicing and testing
US5851845A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1995 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Dec 18, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging semiconductor dice is provided. The package includes a thinned die mounted on a compliant adhesive layer to a substrate. The package is formed by providing a wafer containing a plurality of dice, thinning a backside of the wafer by etching or polishing, attaching the thinned wafer to the substrate, and then dicing the wafer. The semiconductor package can be mounted to a supporting substrate such as a printed circuit board in a chip-on-board configuration. The compliant adhesive layer and substrate of the package eliminate stresses and cracking of the die caused by a thermal mismatch between the die and supporting substrate. In addition, the semiconductor package can be mounted in a flip chip configuration with the substrate for the package protecting a backside of the die from radiation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.