Alan G. Wood
399Patents
80h-index
49Co-inventors
90Inventor score
Filing activity: Sep 30, 1988 → Jan 16, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6235554A | Method for fabricating stackable chip scale semiconductor package | Electricity | 674 | Expired |
| US5739585A | Single piece package for semiconductor die | Emerging Cross-Sectional Technologies | 523 | Expired |
| US6013948A | Stackable chip scale semiconductor package with mating contacts on opposed surfaces | Electricity | 456 | Expired |
| US6841883B1 | Multi-dice chip scale semiconductor components and wafer level methods of fabrication | Electricity | 455 | Expired |
| US5674785A | Method of producing a single piece package for semiconductor die | Emerging Cross-Sectional Technologies | 425 | Expired |
| US6020629A | Stacked semiconductor package and method of fabrication | Electricity | 382 | Expired |
| US5495667A | Method for forming contact pins for semiconductor dice and interconnects | Emerging Cross-Sectional Technologies | 365 | Expired |
| US6097087A | Semiconductor package including flex circuit, interconnects and dense array external contacts | Electricity | 365 | Expired |
| US6114240A | Method for fabricating semiconductor components using focused laser beam | Electricity | 321 | Expired |
| US7393770B2 | Backside method for fabricating semiconductor components with conductive interconnects | Emerging Cross-Sectional Technologies | 312 | Expired |
| US5851845A | Process for packaging a semiconductor die using dicing and testing | Emerging Cross-Sectional Technologies | 303 | Expired |
| US5483741A | Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice | Emerging Cross-Sectional Technologies | 301 | Expired |
| US7498675B2 | Semiconductor component having plate, stacked dice and conductive vias | Electricity | 273 | Active |
| US6107109A | Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate | Electricity | 260 | Expired |
| US5138434A | Packaging for semiconductor logic devices | Electricity | 253 | Expired |
| US5686317A | Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die | Emerging Cross-Sectional Technologies | 245 | Expired |
| US6169329A | Semiconductor devices having interconnections using standardized bonding locations and methods of designing | Electricity | 243 | Expired |
| US6908784B1 | Method for fabricating encapsulated semiconductor components | Electricity | 234 | Expired |
| US4899107A | Discrete die burn-in for nonpackaged die | Physics | 229 | Expired |
| US5593927A | Method for packaging semiconductor dice | Electricity | 223 | Expired |
| US6228687A | Wafer-level package and methods of fabricating | Electricity | 223 | Expired |
| US6294837A | Semiconductor interconnect having laser machined contacts | Electricity | 223 | Expired |
| US5990566A | High density semiconductor package | Electricity | 223 | Expired |
| US5541525A | Carrier for testing an unpackaged semiconductor die | Electricity | 218 | Expired |
| US5408190A | Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die | Electricity | 214 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.