Method of forming a dram cell with a crown-fin-pillar structure capacitor
US5851897A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Nov 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a crown shape capacitor with a plurality of horizontal fins. First, a first polysilicon layer is formed on a semiconductor substrate. A composition layer consists of BPSG and silicon oxide formed on a the first polysilicon layer. Then a contact hole is formed in the composition layer and the first polysilicon layer. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed in the contact hole and the composition layer. Then photolithgraphy and etching process is used to etch the second polysilicon layer, composition layer and first polysilicon layer. A third polysilicon layer is subsequently formed on the second polysilicon layer. An anisotropic etching is performed to etching the second and the third polysilicon layer. Then the composition layer is removed by BOE solution. A dielectric film is then formed along the surface of the first, second and third polysilico…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.