Formation of a self-aligned integrated circuit structures using planarization to form a top surface
US5851916A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 1995 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Nov 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A improved method is provided for forming self-aligned integrated circuit structures, particularly self-aligned contact structures, by providing, on a substrate, raised structures each including an outermost protective layer, and each having a horizontal upper surface extending between substantially vertical lateral surfaces, said horizontal upper surface being horizontal over the entire area therebetween. An etchable layer is formed over and between said raised structures. A photoresist layer is formed on said etchable layer and patterned. Said etchable layer is then anisotropically etched selective to said protective layer to remove said etchable layer from between selected of said raised structures, said horizontal upper surfaces substantially preventing etching at top outer edges of said raised structures and preserving thereby the integrity of the protective layers. A fill layer is then deposited to fill between said selected of said raised structures, forming thereat structures that are self-aligned to said selected of said raised structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.