Method for forming metallization in semiconductor devices with a self-planarizing material

US5854126A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Dirk Tobben · Fishkill, US
• Bruno Spuler · Wappingers Falls, US
• Martin Gutsche · Dorfen, DE
• Peter Weigand · Unterhaching, DE

Key dates

• Filing date: Mar 31, 1997
• Grant date: Dec 29, 1998
• Expiry date: Mar 31, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K2203/0585
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer…