Method for automatically routing circuits of very large scale integration (VLSI)
US5856927A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1995 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | May 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An automated routing tool for routing interconnections between circuit elements, standard cells and/or cell blocks of cell-based designs which incorporates the best features of both currently known gate array routing techniques with currently known cell-based routing techniques. The invention eliminates the disadvantages of permitting the detailed router to adjust the relative positions of the circuit elements, standard cells and/or cell blocks during the detailed routing process. The method employs a topology manager which iteratively compacts the circuit topology while at the same time optimizing the routing of the interconnections among the circuit elements, standard cells and/or cell blocks of the circuit design. The method employs bin-based global routing, which identifies expandable boundaries and which provides input to a compaction routine which expands or contracts the expandable areas in accordance with the result of the global routing process. The detailed routing step is not performed until after the relative positions of the circuit elements, cells and/or cell blocks have been already fixed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.