Method for fabricating a capactior in a DRAM cell

US5858835A · kind A · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventor

• Chi-Hui Lin · Taipei, TW

Key dates

• Filing date: Dec 22, 1997
• Grant date: Jan 12, 1999
• Expiry date: Dec 22, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/712

Abstract

A method for fabricating a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming an insulating layer over the semiconductor substrate; forming a contact opening through the insulating layer to expose a portion of the semiconductor substrate; forming a first polysilicon layer over the insulating layer and filling in the contact opening to electrically contact the semiconductor substrate; patterning the first polysilicon layer to the insulating layer surface, thereby forming a trench for defining a capacitor region; forming a thin polysilicon layer with a rugged surface over the first polysilicon layer and the insulating layer; forming a mask layer over the thin polysilicon layer, wherein the mask layer has a smaller thickness in the trench bottom than in other regions; removing the mask layer in the trench bottom through an anisotropical etch step; removing the uncovered portions of the thin polysilicon layer to expose the insulating layer surface; removing the mask layer, thereby forming a storage electrode consisting of the thin polysilicon layer and the first polysilicon layer; forming a dielectric layer over the storage electrode and th…