Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate
US5858848A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Oct 24, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate. A dielectric, preferably nitride, is deposited by CVD across the exposed LDD areas of the semiconductor substrate, the sacrificial dielectric, and the gate conductor. The nitride is removed down to a plane level with the upper surface of the gate conductor. The sacrificial dielectric may the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.