Data holding circuit and buffer circuit
US5859800A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Oct 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356173
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.