Multilevel transistor fabrication method having an inverted, upper level transistor

US5863818A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Daniel Kadosh · Austin, US
• Mark I. Garnder · Mabank, US
• Robert Paiz · Austin, US

Key dates

• Filing date: Oct 8, 1996
• Grant date: Jan 26, 1999
• Expiry date: Oct 8, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/01

Abstract

A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor. The inverted, upper level transistor thereby comprises a gate conductor residing in an elevation level below the gate dielectric and source/drain implants of that transistor. Direct coupling of one transistor gate conductor to another transistor gate conductor not only minimizes the overall rout…