Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
US5864565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Jan 26, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3193
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit and method for compressing test stimuli to one test output signal during a test mode. The test output signal is driven from one input/output node of the semiconductor integrated circuit to a test station through a load board interface. Buffer circuitry on the semiconductor integrated circuit drive a high impedance to the input/output nodes of the integrated circuit during the test mode. The load board interface allows a single test station to receive test output signals from a plurality of semiconductor integrated circuits of the invention during the test mode, thereby allowing one test station to simultaneously test a plurality of circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.